Digital Hardware Design

FPGA Based

At CARE we have a rich portfolio of designing FPGA-based systems from concept to implementation. We have designed FPGA-based systems for Nortel Networks, NEC, STM wireless. Our complex real-time systems consist of micro-controller, digital signal processor and FPGA. We specialize in optimally partitioning the design into HW/SW modules. The HW modules are mapped as fully parallel, time-shared, or micro-coded state machines on FPGA.


CARE team has designed three highly complex SoCs for technologies ranging .18 micron to .13 micron. CARE universal SoC platform can give a jump-start to any complex SoC design. The platform has SDRAM memory I/Os, DMA, CPU interfaces, HW embedded RTOS for multiprocessors, inter processor communication platform.


CARE team specializes in mapping computationally intensive algorithms in HW. The team has experience in mapping algorithms as programmable processor with enough flexibility to map an entire family of these algorithm on the hardware.

Viterbi decoder with puncturing

Reed Solomon encoder and decoder

Multi Channel DTMF gererator for VoIP applications

Speech Coders , G.711, G.729a, G.72

Data modems

Encryption, Decryption, Key exchange


Motion estimation and compensation

Interfaces for PCI/PCI-X ,DDR memmory MIPS/ARM processors etc

Network Processor

CARE team has designed and developed high throughput Network Processor and its peripherals. The salient features of the processor are the following:

  • OC-3 rate Real Time Deep Packet Processing and OC-12 Aggregation and Forwarding
  • QoS, Traffic Management and IP Sec with support for simultaneous connections to ATM, IP, TDM, and back-plane switching fabric

On-chip supported interfaces include:

  • GMAC, POS-II, UTOPIA-II, TDMIO, PCI-X, DDR Memory Interfaces
  • On-chip Multiple RISC Cores and Cross Connect DMA
  • Complete tool-suite for application software development including C Compiler, Bit-exact hardware simulator, hardware debugger through J-tag

DSP Processor

A traditional DSP comes with a fixed instruction set. The design is focused on traditional DSP applications with basic DSP functionality of Multiply Accumulate (MAC) operation. The trend is to design a Very Long Instruction Word (VLIW) instruction set and provide multiple MAC operations capabilities in the hardware. There is a range of processors available in the market with these capabilities but they only suit to general class of applications as they focused a broad range of applications. These processors are not optimized for specific applications and hence the performance to cost ratio of the resultant systems is not always optimal. CARE team has designed several application specific DSPs which outperform general purpose DSPs in performance and cost.


Security Processor <

CARE team has experience in designing very high data rate IPSec processing components and complete HW/SW VPN solution. These components are easily pluggable in any networking or computing system as soft macros. These components off load the main processor from computationally intensive operations of IP security protocols. A list of these components are as follows:

  • DES, 3DES and AES based Encryption/Decryption 
  • DH, RSA and DSA based key generation
  • Main and aggressive IKE modes implemented for RSA Signatures, as well as RSA Private and Public Key generation methods
  • Remote user ID Authentication to protect against “Man in the Middle Attacks”
  • SHA, MD5, RIPEMD-128/192, TIGER (with and without HMAC) based Authentication


Media Processor

CARE team has designed and developed highest density Media Processor for Carrier Class Media Gateway Applications. The Media Processor provides:

  • Three levels of parallelism for high-density and low-power media processing i.e.:
    • Scheduler 
    • Media Switch
    • Processing Engine
  • Advanced memory management for high throughput
  • Suport for block-level and sample-by-sample processing
  • Rich Media Instruction Set Architecture
  • Dynamic swapping of software components at run time
  • Non-service affecting remote software upgrades
  • Remote Debug and Development
  • Sleep unused resouces for low power consumption
  • Fully programmable solution: LEC, Voice Encoder/Decoder, etc
  • Software compatibilty at the API level for chip upgrades
  • Advanced Integrated Development Environment